T-Ram cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same

ABSTRACT

A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.

FIELD OF THE INVENTION

[0001] This invention relates to the field of integrated circuit (IC)design. Specifically, the invention relates to a Thyristor Random AccessMemory (T-RAM) cell and method for fabricating the same. Morespecifically, the invention relates to a T-RAM cell having a buriedvertical thyristor, a stacked pseudo-TFT transfer gate and a planar cellstructure, and method for fabricating the same.

BACKGROUND OF THE INVENTION

[0002] A low-power, high-speed and high-density negative differentialresistance (NDR) based (NDR-based) SRAM cell which can provide DRAM-likedensities at SRAM-like speeds has been proposed by Farid Nemati andJames D. Plummer in “A Novel High Density, Low Voltage SRAM Cell with aVertical NDR Device,” 1998 Symposium on VLSI Technology Digest ofTechnical Papers, IEEE, pages 66-67, 1998.

[0003] The memory device structure is shown by FIG. 1 and is designatedby reference numeral 10; the memory device structure is called aThyristor-based Random Access Memory (T-RAM) cell. The T-RAM device ormemory cell 10 consists of a thin vertical pnpn thyristor 12 with asurrounding NMOS gate 14 as the bistable element and a planar nMOSFET asthe access transistor 16. The circuit schematic of the T-RAM cell 10 isshown by FIG. 2.

[0004] To access the T-RAM cell 10, two wordlines are necessary. Thefirst wordline WL1 is used to control an access gate of the transfernMOSFET device 16, while the second wordline WL2 is the surrounding NMOSgate 14 which is used to control the switch of the vertical pnpnthyristor 12. The thyristor 12 is connected to a reference voltage Vref.The second wordline WL2 improves the switching speed of the thyristor 12from 40 ns to 4 ns with a switching voltage. A bitline BL connects theT-RAM cell 10 to a sense amplifier for reading and writing data from andto the T-RAM cell 10. The T-RAM cell 10 exhibits a very low standbycurrent in the range of 10 pA.

[0005] When writing a “high”, the bitline BL is set at low, and bothwordlines WL1, WL2 are switched on. At this moment, the thyristor 12behaves like a forward biased pn diode. After a write operation, bothgates are shut off, and a “high” state is stored in the thyristor 12. Ina read operation, only the first wordline WL1 is activated, a large “on”current will read on the bitline BL through the access gate. Whenwriting a “low”, the bitline BL is set at “high” state, and bothwordlines WL1, WL2 are switched on. At this moment, the thyristor 12behaves like a reverse biased diode. After the write operation, bothgates are shut off, and a “low” state is stored in the thyristor 12.Similarly, in a consequence read, a very low current will be detected onthe bitline BL. Further details of the operation of the T-RAM cell 10and its gate-assisted switching are described in Nemati et al.; thecontents of which are incorporated herein by reference.

[0006] A T-RAM array having a plurality of T-RAM cells 10 hasdemonstrated a density equivalent to that of DRAM arrays and a speedequivalent to that of SRAM arrays. Hence, the T-RAM array providesadvantages afforded by both SRAM and DRAM arrays. These advantages makeT-RAM an attractive choice for future generations of high speed,low-voltage, and high-density memories and ASICs.

[0007] However, there are several drawbacks of the T-RAM cell 10. First,there is the requirement of forming the thyristor 12 having a verticalpillar on a substrate during a fabrication process. Difficulties arisein controlling the dimensions of the vertical pillar and reproducingthese dimensions for each T-RAM cell 10 in the T-RAM array. Second, dueto the existence of a vertical thyristor 12 in each T-RAM cell 10, eachT-RAM cell 10 is not planar and therefore difficult to scale. Third, itis difficult to control the dimension while forming the surrounding basegate around the base of each vertical thyristor 12. Fourth, each T-RAMcell is fabricated prior to or after fabricating any other devices, suchas p-MOS and n-MOS support devices (i.e., sense amplifiers, wordlinedrivers, column and row decoders, etc.), which results in extrafabrication steps, thereby increasing thermal budget and manufacturingcost. Finally, due to these drawbacks, the resulting T-RAM cell 10cannot be smaller than 8F² and the cost of fabricating a T-RAM array ishigh.

SUMMARY

[0008] An aspect of the present invention is to provide a T-RAM arrayhaving a planar cell structure for overcoming the disadvantages of theprior art.

[0009] Another aspect of the present invention is to provide a T-RAMarray having a plurality of T-RAM cells, wherein each of the pluralityof T-RAM cells has a planar cell structure, a buried vertical thyristorand a horizontally stacked pseudo-TFT (Thin-Film Transistor) transfergate.

[0010] Also, another aspect of the present invention is to provide amemory system having a plurality of T-RAM cells arranged in an array,wherein each of the plurality of T-RAM cells has a planar cellstructure, a buried vertical thyristor and a horizontally stackedpseudo-TFT transfer gate.

[0011] Further, another aspect of the present invention is to provide amethod for fabricating a high-density, high-yield and low-cost T-RAMarray having a plurality of T-RAM cells and a planar cell structure on aSOI substrate. Each of the plurality of T-RAM cells has a planar cellstructure, a buried vertical thyristor and a horizontally stacked pseudotransfer gate.

[0012] Another aspect of the present invention is to provide a methodfor fabricating a T-RAM array which improves performance and yield, andreduces cost and thermal budget.

[0013] Other aspects of the present invention is a method forfabricating a surrounded base gate of a buried vertical thyristor of aT-RAM cell and a method of making contact with a horizontally stackedpseudo-TFT transfer gate. Another aspect of the present invention is amethod of forming a high-quality, self-aligned pseudo-TFT transfer gateof a T-RAM cell.

[0014] Accordingly, in an embodiment of the present invention, a T-RAMarray is presented having a planar cell structure and a plurality ofT-RAM cells where each T-RAM cell is planar and has a buried verticalthyristor and a horizontally stacked pseudo-TFT transfer gate. Theinventive structure of each T-RAM cell results in higher performance atlow voltage, e.g., Vdd=1V.

[0015] In another embodiment of the present invention, a memory systemis presented having a plurality of T-RAM cells arranged in an array.Each of the T-RAM cells in the array has a planar cell structure, aburied vertical thyristor and a horizontally stacked pseudo-TFT transfergate.

[0016] Further still, in another embodiment of the present invention, amethod is presented for fabricating a T-RAM array having a planar cellstructure. Each of the T-RAM cells in the T-RAM array has a buriedvertical thyristor and a horizontally stacked pseudo-TFT transfer gate.The method entails forming a surrounded base gate of the buried verticalthyristor and making contact with the horizontally stacked pseudo-TFTtransfer gate. The method also entails forming a high-quality,self-aligned stacked pseudo-TFT transfer gate for each of the T-RAMcells. Preferably, the T-RAM array is built on a semiconductorsilicon-on-insulator (SOI) wafer to reduce junction capacitance andimprove scalability.

BRIEF DESCRIPTION OF THE FIGURES

[0017]FIG. 1 illustrates the device structure of a prior art T-RAM cell;

[0018]FIG. 2 is a circuit diagram of the prior art T-RAM cell;

[0019]FIG. 3 is a cross-sectional view of a portion of a semiconductorsilicon-on-insulator (SOI) wafer having a buried oxide layer and aseries of layers for fabricating T-RAM cells according to the presentinvention;

[0020] FIGS. 4-11 are cross-sectional views illustrating a preferredprocess for fabricating a T-RAM cell according to the present invention;

[0021]FIG. 12 is a top phantom view of a portion of a T-RAM arrayshowing the T-RAM cell fabricated according to the present invention;

[0022]FIG. 13 is a cross-sectional view of a T-RAM cell according to thepresent invention; and

[0023]FIG. 14 is a top phantom view of a portion of the T-RAM arrayshowing a plurality of T-RAM cells fabricated according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention provides a T-RAM array having a planar cellstructure and a plurality of T-RAM cells. Each of the T-RAM cells of theinventive T-RAM array is planar and includes a buried vertical thyristorand a horizontally stacked pseudo-TFT transfer gate. Hence, the T-RAMarray of the present invention provides for less control duringmanufacturing, and is planar and more scalable than prior art T-RAMarrays. The present invention also provides a preferred method forfabricating the T-RAM array to reduce cost and thermal budget, whileincreasing performance, density and yield.

[0025] Unlike a DRAM cell, the state of a T-RAM cell does not depend onthe amount of charge stored in a capacitor, rather it depends on theinternal programming state of the thyristor. In order to maintain theinternal programming state of the thyristor, a low DC current ispermitted to constantly flow through the thyristor. Similar to an SRAMcell, when the state of the T-RAM cell is stored and latched, a smallleakage current flows from Vdd to ground via off-state devices. For anSRAM cell with a resistive load or TFT load, the DC leakage current isrequired in order to maintain the state of the SRAM cell.

[0026] In the present invention, in order to save area, a pseudo-TFT isused as the transfer gate for the inventive T-RAM cell. The pseudo-TFTtransfer gate can be fabricated on top of a thyristor of the inventiveT-RAM cell which causes the resulting cell area to be very small. Theoff-state leakage current of the pseudo-TFT transfer gate may be higherthan that of a conventional device. However, it is acceptable to beimplemented for the inventive T-RAM array disclosed herein, ifperformance of the T-RAM array is increased and size of the TRAM arrayis decreased, for a slightly higher standby power. Nonetheless, such astandby current exists in the thyristor of a T-RAM cell whether or notthe TFT is used as the transfer gate.

[0027] The stacked pseudo-TFT transfer gate of the inventive T-RAM isfabricated using a lateral overgrowth epi technique via a single crystalseed area. The quality and performance of the stacked pseudo-TFTtransfer gate is significantly better than that of a conventional TFTdevice.

[0028]FIG. 3 is a cross-sectional view of a portion of a semiconductorsilicon-on-insulator (SOI) wafer having a buried oxide layer and aseries of layers for fabricating T-RAM cells according to the presentinvention. The wafer is designated by reference numeral 100. It iscontemplated that other types of semiconductor wafers besidessemiconductor SOI wafers, such as semiconductor bulk wafers, can be usedfor fabricating T-RAM cells according to the present invention.

[0029] With reference to FIG. 3, a semiconductor SOI wafer 100 having aburied oxide layer 102 and a p+ layer 104 is used as the substrate toform the T-RAM cells. The p+ layer 104 is preferably a p+ silicon layerdoped with a dosage of between 2E14 cm² to 8E14/cm² of boron. The p+layer 104 will be used to form the p terminal of the thyristor whichwill be tied to a reference voltage (about one volt) during operation.The p+ layer 104 will also be used as the seed for epitaxial growth asdescribed below.

[0030] Over the SOI wafer 100, a predetermined thickness, approximately4000 Å, of nitride and oxide are deposited to form a nitride-oxide layer106 having a nitride layer 106 a, approximately 1000 Å, and an oxidelayer 106 b, approximately 3000 Å. A predetermined thickness,approximately 100 to 300 Å, of nitride is deposited over the oxide layer106 b to form a nitride layer 108. The total thickness of thenitride-oxide layer 106 is approximately equal to the height of thethyristor (see FIG. 11).

[0031] A description of the preferred method for fabricating a T-RAMcell of the T-RAM array will now be provided. The same fabricationmethod is used for simultaneously fabricating all of the T-RAM cells ofthe T-RAM array. With reference to FIGS. 4-11 there are showncross-sectional views of the semiconductor wafer 100 for fabricating theT-RAM cell.

[0032] With reference to FIG. 4, a first mask 110 is positioned over thewafer 100. The nitride layer 108 and the nitride-oxide layer 106 areetched to define a thyristor region 112. The height of the thyristorregion 112 determines the height of the gate surrounding the base regionof the thyristor (see FIG. 11).

[0033] With reference to FIG. 5, an in-situ n+ doped gate polysiliconlayer 114 is formed. The dimension on the left of the polysilicon layer114 is made wider than the dimension on the right of the polysiliconlayer 114 because the wider region will be used for gate contact asshown by FIG. 12.

[0034] With reference to FIG. 6, a spacer etching process is performedto form spacer gates 116 a, 116 b. A gate dielectric formation processis then performed on the outer surface of the spacer gates 116 a, 116 bto form a dielectric layer 118 thereon. The gate dielectric formationprocess may entail performing an oxidation process followed by a thinoxy-nitride deposition process as known in the art.

[0035] With reference to FIG. 7, an etching process is performed toremove the exposed nitride layer 106 a to the surface of the p+ layer104 to form a thyristor region 119.

[0036] With reference to FIG. 8, an epitaxial growth procedure isperformed to form an n-p-n layer 120 having an n layer 120 a, a p layer120 b and an n+ layer 120 c. The n-p-n layer 120 is formed using aconventional selective epi technique to precisely control the thicknessand the doping concentration of each layer.

[0037] The n layer 120 a is preferably formed by epi with an n-typearsenic impurity with doping concentration of between 2E13/cm² and8E14/cm². The p layer 120 b is preferably formed by epi with a p-typeboron impurity with doping concentration of between 4E13/cm² and1E14/cm². The n+ layer 120 c is preferably formed by epi of an n-typearsenic impurity with doping concentration of between 8E14/cm² and3E15/cm².

[0038] With reference to FIG. 9, an epitaxial lateral overgrowthprocedure with a p-doping is performed to form an epi layer 122 forforming the body of the horizontally stacked pseudo-TFT transfer gate.The epi layer 122 is mostly single crystalline, since it uses the n+layer 120 as the seed material. The epi layer 122 is capped with adielectric film 124, such as oxide and/or nitride.

[0039] With reference to FIG. 10, the stacked pseudo-TFT transfer gateregion is defined by a conventional masking process. A sacrificialinsulating film 126, such as CVD oxide, glass, or polymer is depositedover the structure. A Ddamascene gate process is used to form two gates128, 130. After a chem-mech polish, the upper surfaces of the two gates128, 130 are co-planar.

[0040] With reference to FIG. 11, the sacrificial insulating film 126 isstripped. An n+ dopant is implanted to create n+ regions 132 a, 132 b,thereby forming the source and drain regions of the stacked pseudo-TFTtransfer gate. The n+ dopant is preferably formed by using an n-typearsenic implant at an energy in the range of 2 to 15 KeV and a dosage ofbetween 8E14/cm² and 3E15/cm². Spacers 136 are then formed to fullyfabricate two wordline gates WLL1, WLL2 of a T-RAM memory cell 200.

[0041] With reference to FIG. 12 there is shown a top phantom view ofthe T-RAM cell 200 fabricated according to the present invention andshowing the connections to the two wordlines WLL1, WLL2 and a bitlineBL. The T-RAM cell 200 has a size measurement of 8F², where F is theminimal printable feature size. It is appreciated that one skilled inthe art can modify the process described herein to realize similarlystructured T-RAM cells having a size measurement of less than 8F².

[0042] With continued reference to FIG. 12, one of the two wordlines,i.e., wordline WLL2, contacts the bitline BL via a metallic bitlinecontact 138. The metallic bitline contact 138 is provided in order forthe wordline WLL2 to contact the bitline BL and for maintaining adistance “D” from the wordlines WLL1, WLL2 (see FIG. 13).

[0043] The heavy line box which is identified by the letters “TR” inFIG. 12 designates the thyristor region of a buried p-n-p verticalthyristor 210. The thyristor region TR contacts wordline WLL1 and issurrounded by a surrounded gate 140. The surrounded gate 140 contactsthe wordline WLL2 by a contact stud 138 and is formed by spacer gates116 a, 116 b. The box identified by the letters “TGR” designates thetransfer gate region of the horizontally stacked pseudo-TFT transfergate 220. The bitline BL contacts n+ region 132 b of the stackedpseudo-TFT transfer gate 220 via contact stud 138.

[0044]FIG. 14 is a top phantom view of a portion of a T-RAM arraydesignated by reference numeral 300 showing a plurality of T-RAM cells200 a-d fabricated according to the present invention. FIG. 14 alsoshows the location of the first and second left wordlines WLL1, WLL2,the location of first and second right wordlines WLR1, WLR2, and thelocation of first and second bitlines BL1, BL2. A first pair of adjacentcells 200 a, 200 b of the array 300 share the same bitline contact 138b. A second pair of adjacent cells 200 c, 200 d of the array 300 sharethe same bitline contact 138 e.

[0045] With the method of the present invention, minimal process stepsand mask levels are required to fabricate planar T-RAM cells 200 of aT-RAM array on bulk or SOI which results in a significant saving inmanufacturing cost and provides a better thermal budget over prior artmethods. The buried p-n-p vertical thyristor 210 and the horizontallystacked pseudo-TFT transfer gate 220 of each T-RAM cell 200 aresimultaneously fabricated in a very compact dimension to reducemanufacturing cost and time, while providing reliable T-RAM cells 200.Additionally, the planar T-RAM array structure is easy to fabricate,since the depth of focus for the lithographic tools and metalinterconnects is easier to handle than the three-dimensional verticaldevice of the prior art T-RAM structure (see FIG. 1).

[0046] By sharing etching and diffusion steps, thermal budget is tightlycontrolled. This leads to better device quality and reliability.Otherwise, extra thermal steps needed to form T-RAM cells will cause thejunction depth of the normal device deeper which leads to higherjunction capacitance and poorer performance. Additionally, the T-RAMcells having the surrounded gate structure which is fabricated accordingto the inventive method are suitable for future scaling andmetallization than the prior art T-RAM cells which have the verticalthyristor. Further, the structure of the present invention is fullyplanar and results in higher performance at low voltage (e.g., Vdd=1V).

[0047] Further, the method of the present invention provides twin-towerT-RAM cells having a size of less than or equal to 8F². Accordingly, thedensity of a T-RAM array is small, while the yield and memoryperformance is high.

[0048] A T-RAM array having a plurality of T-RAM cells 200 according tothe present invention can be provided within a central processing unitor other type of processor to provide a reliable and high performancememory system.

[0049] What has been described herein is merely illustrative of theapplication of the principles of the present invention. Otherarrangements and methods, such as using different substrates, may beimplemented by those skilled in the art without departing from the scopeand spirit of this invention.

We claim:
 1. A memory system comprising a plurality of T-RAM cellsarranged in an array, wherein each of the plurality of T-RAM cellsincludes a thyristor region beneath at least a portion of a transfergate region.
 2. The memory system according to claim 1, wherein thethyristor region includes a buried vertical thyristor and the transfergate region includes a horizontally stacked pseudo-TFT transfer gate. 3.The memory system according to claim 1, wherein each of the plurality ofTRAM cells has a size of less than or equal to 8F².
 4. The memory systemaccording to claim 1, wherein the plurality of T-RAM cells arefabricated on a semiconductor SOI or bulk wafer.
 5. The memory systemaccording to claim 1, wherein a base of the thyristor region issurrounded by a vertical surrounded gate.
 6. The memory system accordingto claim 5, wherein the vertical surrounded gate contacts a wordline. 7.The memory system according to claim 1, wherein the thyristor region andthe transfer gate region are connected by a lateral epitaxial grown n+region.
 8. The memory system according to claim 2, wherein a bitlinecontacts a junction of the stacked pseudo-TFT transfer gate.
 9. Thememory system according to claim 2, wherein the stacked pseudo-TFTtransfer gate contacts a wordline.
 10. The memory system according toclaim 1, wherein each of the plurality of T-RAM cells includes structurefor the traversal of at least two wordlines there through.
 11. Thememory system according to claim 2, wherein a vertical surrounded gateis aligned with a base region of the buried vertical thyristor.
 12. AT-RAM array comprising: a plurality of T-RAM cells, wherein each of theplurality of T-RAM cells includes a thyristor region beneath at least aportion of a transfer gate region.
 13. The array according to claim 12,wherein the thyristor region includes a buried vertical thyristor andthe transfer gate region includes a horizontally stacked pseudo-TFTtransfer gate.
 14. The array according to claim 12, wherein each of theplurality of T-RAM cells has a size of less than or equal to 8F². 15.The array according to claim 12, wherein the plurality of T-RAM cellsare fabricated on a semiconductor SOI or bulk wafer.
 16. The arrayaccording to claim 12, wherein a base of the thyristor region issurrounded by a surrounded gate.
 17. The array according to claim 12,wherein each of the plurality of T-RAM cells includes structure for thetraversal of at least two wordlines there through.
 18. A method forfabricating a T-RAM array having a plurality of T-RAM cells, the methodcomprising the steps of: providing a semiconductor wafer; fabricating athyristor region having a thyristor for each of the plurality of T-RAMcells over the semiconductor wafer; and fabricating a surrounded gatefor each of the plurality of T-RAM cells, wherein the surrounded gate isaligned with a base region of the thyristor; fabricating a transfer gateregion having a transfer gate for each of the plurality of TRAM cellsover at least a portion of the thyristor region.
 19. The methodaccording to claim 18, wherein each of the plurality of T-RAM cells hasa size of less than or equal to 8F².
 20. The method according to claim18, wherein the semiconductor wafer is a semiconductor SOI or bulkwafer.
 21. The method according to claim 18, wherein the thyristor is avertical thyristor and the transfer gate is a pseudo-TFT transfer gate.22. The method according to claim 18, further comprising the step offabricating first and second wordlines, wherein the first wordlinecontacts the surrounded gate and the second wordline is integral withthe transfer gate.
 23. The method according to claim 18, furthercomprising the step of fabricating a plurality of bitline contactsthroughout the T-RAM array; and fabricating a plurality of bitlines anda plurality of bitline contacts contacting a respective one of theplurality of bitlines, wherein each of the plurality of bitline contactsconnects the respective one of the plurality of bitlines to a junctionof the transfer gate.
 24. The method according to claim 18, furthercomprising the step of providing three layers on the semiconductor waferprior to the step of fabricating the thyristor region, wherein a firstlayer is provided on top of a buried oxide layer and is a p-type layerand a second layer is provided on top of the first layer, said secondlayer is a nitride-oxide layer having a nitride layer below an oxidelayer.
 25. The method according to claim 24, wherein the step offabricating the thyristor region having the thyristor for each of theplurality of T-RAM cells over the semiconductor wafer includes the stepsof: providing a mask over the semiconductor wafer; etching the oxidelayer of the second layer to form etched regions over the nitride layer;depositing polysilicon within the etched regions; etching thepolysilicon to form a pair of spacer gates for each of the plurality ofT-RAM cells; etching the nitride layer of the second layer to thesurface of the first layer to shape the thyristor region; and growing ann-p-n layer within the thyristor region to form the thyristor.
 26. Themethod according to claim 25, wherein the step of growing the n-p-nlayer includes the steps of: fabricating a first n-type layer over thefirst layer using a first n-type doping implant; fabricating an p-typelayer over the first n-type layer using a p-type doping implant; andfabricating a second n-type layer over the p-type layer by using asecond n-type doping implant.
 27. The method according to claim 26,wherein the step of fabricating the first n-type layer includes the stepof using n-type doping with a dosage of between 2E13/cm² and 8E14/cm²;wherein the step of fabricating the p-type layer includes the step usinga p-type doping with a dosage of between 4E13/cm² and 1E14/cm²; andwherein the step of fabricating the second n-type layer includes thestep of using an n-type doping with a dosage of between 8E14/cm² and3E15/cm².
 28. The method according to claim 18, wherein the step offabricating the transfer gate region having the transfer gate for eachof the plurality of T-RAM cells over at least a portion of the thyristorregion includes the steps of: fabricating an epi layer over thethyristor region; providing a dielectric film over the epi layer;depositing an insulating film over the dielectric film; forming twogates within the insulating film; and implanting an n+ dopant within theepi layer to form source and drain regions for the transfer gate.